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          云合智網

          ASIC Design Engineer

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            ¥3k
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          • 30萬-60萬/年
          • 上海
          • |
          • 工作經驗不限
          • |
          • 本科
          • |
          • 全職

          職位誘惑: 年終獎金,五險一金,福利好,老板nice,十五薪,股票期權,技術領先,節日禮物

          發布時間: 2021-03-05發布

          職位描述

          Responsibilities
          1.Design high performance and high-quality ASIC modules from specification to RTL implementation
          2.Responsible for module level spec creation, RTL coding, Lint/CDC check, synthesis, formal check, and timing closure.
          3.Co-work with Verification team/SW team to validate the chip design. 
          4.Participate in lab bring up and validation, debug and support
          5.Real work location is not confined to Shanghai
          Skill requirement
          1.>1 year hands-on experience in ASIC/FPGA digital design. 
          2.Master’s degree desired, Bachelor's degree in CS/EE is required. 
          3.Hands-on experience on Verilog HDL coding and verification
          4.Experience of high-performance ASIC design
          5.Knowledge of network application is a plus 
          6.Knowledge of ARM subsystem is a plus 
          7.Knowledge of System Verilog and UVM verification is a plus 
          8.Good at Unix/Perl/Python scripting is a plus
          9.Highly motivated, positive, detail oriented and responsible
          10.Good team player and good communication skills
          11.Salary negotiable
           

          職位發布者

          杭州云合智網技術有限公司

          HR

          7天

          簡歷處理用時

          100%

          簡歷及時處理率

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